15.3 Floating-Point General Registers (FGRs)
Load and Store Operations
When FR = 0, floating-point load and stores operate as follows:
- A doubleword load or store is handled the same as if the FR bit was set to 1, as long as the register selected is even (0, 2, 4, etc.).
- If the register selected is odd, the load/store is invalid.
These operations are shown in Figure 15-3. Singleword loads/stores to even and odd registers are also shown.
Figure 15-3 Loading and Storing Floating-Point Registers in 16-Register Mode
NOTE: Move (MOV) and conditional move (MOVC, MOVN, MOVZ are included in these arithmetic operations, although no arithmetic is actually performed.
When FR = 1, floating-point load and stores operate as follows:
- Single-precision operands are read from the low half of a register, leaving the upper half ignored. Single-precision results are written into the low half of the register. The high half of the result register is architecturally undefined; in the R10000 implementation, it is set to zero.
- Double-precision arithmetic operations use the entire 64-bit contents of each operand or result register.
Because of register renaming, every new result is written into a temporary register, and conditional move instructions select between a new operand and the previous old value. The high half of the destination register of a single-precision conditional move instruction is undefined (shown in Figure 15-5), even if no move occurs.
Singleword and doubleword loads and stores with the FPU in 32-register mode (FR=1) are shown in Figure 15-4.
Figure 15-4 Loading and Storing Floating-Point Registers in 32-Register Mode
Doubleword load, store and move to/from instructions load or store an entire 64-bit floating-point register, as shown in Figure 15-5.
Figure 15-5 Operators on Floating-Point Registers
In MIPS I and MIPS II ISAs, all arithmetic instructions, whether single- or double-precision, are limited to using even register numbers. Load, store and move instructions transfer only a single word. Even and odd register numbers are used to access the low and high halves, respectively, of double-precision registers. When storing a floating-point register (SWC1 or MFC1), the processor reads the entire register but writes only the selected half to memory or to an integer register.
Because the register renaming scheme creates a new physical register for every destination, it is not sufficient just to enable writing half of the Floating-Point register file when loading (LWC1 or MTC1); the unchanged half must also be copied into the destination. This old value is read using the shared read port, it is then merged with the new word, and the merged doubleword value is written. (A write to the register file writes all 64 bits in parallel.)
When instructions are renamed in MIPS I or II, the low bit of any FGR field is forced to zero. Thus, each even/odd logical register number pair is treated as an even-numbered double-precision register. Odd numbered logical registers are not used in the mapping tables and dependency logic, but they remain mapped to their latest physical registers.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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